A DSP-BASED PARALLEL ARCHITECTURE FOR NEURAL-NETWORK SIMULATION

This paper presents an analysis of the characteristics a neural network (NN) simulator has to possess, providing a generally valid modular approach to its design. The hardware architecture proposed for the neural network simulator is a multiprocessor common bus architecture with centralized control. Several processing units (PEs) are connected to a common bus and comprise a DSP a work memory and a hardware communication interface for access to the common bus. Particular attention will be paid to the fault tolerance capabilities the architecture has to possess. More specifically, the paper will deal with the problem of recovering the system from a coherent state of knowledge and reconfiguring it. Finally, the paper presents an analysis of the performance of the architecture, highlighting how the performance is affected by the diagnostic tests needed to locate and detect faults.