A graphene FET (GFET), where the active area is made of monolayer large-area graphene, is simulated including a full 2-D Poisson equation and a drift-diffusion model with mobilities deduced by a direct numerical solution of the semiclassical Boltzmann equations for charge transport by a suitable discontinuous Galerkin approach. The critical issue in a GFET is the difficulty of fixing the OFF state which requires an accurate calibration of the gate voltages. In this article, we propose and simulate a GFET structure which has well-behaved characteristic curves similar to those of conventional (with gap) semiconductor materials. The introduced device has a clear off region and can be the prototype of devices suited for postsilicon nanoscale electron technology. The specific geometry overcomes the problems of triggering the minority charge current and gives a viable way for the design of electron devices based on large area monolayer graphene as a substitute of standard semiconductors in the active area. The good FET behavior of the current versus the gate voltage makes the simulated device very promising and a challenging case for experimentalists, even if it is crucial to better understand the resistance effect of charge carriers at the contact-graphene region.
An Efficient GFET Structure
Nastasi G.;Romano V.
2021-01-01
Abstract
A graphene FET (GFET), where the active area is made of monolayer large-area graphene, is simulated including a full 2-D Poisson equation and a drift-diffusion model with mobilities deduced by a direct numerical solution of the semiclassical Boltzmann equations for charge transport by a suitable discontinuous Galerkin approach. The critical issue in a GFET is the difficulty of fixing the OFF state which requires an accurate calibration of the gate voltages. In this article, we propose and simulate a GFET structure which has well-behaved characteristic curves similar to those of conventional (with gap) semiconductor materials. The introduced device has a clear off region and can be the prototype of devices suited for postsilicon nanoscale electron technology. The specific geometry overcomes the problems of triggering the minority charge current and gives a viable way for the design of electron devices based on large area monolayer graphene as a substitute of standard semiconductors in the active area. The good FET behavior of the current versus the gate voltage makes the simulated device very promising and a challenging case for experimentalists, even if it is crucial to better understand the resistance effect of charge carriers at the contact-graphene region.File | Dimensione | Formato | |
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