A Charge Loss Aware Advanced Model of Dickson Voltage Multipliers

In this paper an advanced and accurate model of the Dickson Voltage Multiplier (DVM) accounting for charge-loss nonidealities, like reverse and substrate currents of the charge transfer devices, is proposed. Analytical equations for the single current loss and the various metrics are given. In particular, by inspection of the open-circuit output voltage, it is shown that such currents limit the range of the suitable clock frequency, suggesting the introduction of a further switching limit, namely deep slow switching limit, which is not predictable by the well-known models. Gathered results can be fruitfully exploited to improve the design accuracy of the DVMs for low-voltage, low-power applications. Simulation using SPICE and measurement results on silicon prototypes implemented in 130-nm HV-CMOS and a 65-nm standard CMOS technology confirm the accuracy of the proposed model with a maximum error of 5.5%.