This paper presents and discusses two Dickson charge pumps that are capable of working with a supply voltage lower than the MOS threshold voltage and are particularly suited for energy-constrained applications. Specifically, the paper includes a theoretical analysis of a previous topology introduced by the authors, and then it discusses a novel topology which solves drawbacks of the previous one. The paper also includes a comparison with other conventional topologies, namely the latched and the four-phase charge pumps, that shows the inherent advantage of the proposed solutions also in the range of input values higher than the MOS threshold voltage. 2-, 4-, and 6-stage versions of the conventional and proposed CPs have been fabricated in a 65-nm standard CMOS technology having a MOS threshold voltage equal to about 440 mV. Experimental results confirm the analytical predictions since the proposed topologies work at input voltage equal to 300 mV with a current load equal to 20 $\mu$ A and also confirm the advantages of the two proposed solutions in terms of settling time, output current drivability and output power density for voltages slightly higher (450 mV) than the MOS threshold voltage.
Very-Low-Voltage Charge Pump Topologies for IoT Applications
Ballo A.
Primo
;Grasso A. D.;Palumbo G.
2023-01-01
Abstract
This paper presents and discusses two Dickson charge pumps that are capable of working with a supply voltage lower than the MOS threshold voltage and are particularly suited for energy-constrained applications. Specifically, the paper includes a theoretical analysis of a previous topology introduced by the authors, and then it discusses a novel topology which solves drawbacks of the previous one. The paper also includes a comparison with other conventional topologies, namely the latched and the four-phase charge pumps, that shows the inherent advantage of the proposed solutions also in the range of input values higher than the MOS threshold voltage. 2-, 4-, and 6-stage versions of the conventional and proposed CPs have been fabricated in a 65-nm standard CMOS technology having a MOS threshold voltage equal to about 440 mV. Experimental results confirm the analytical predictions since the proposed topologies work at input voltage equal to 300 mV with a current load equal to 20 $\mu$ A and also confirm the advantages of the two proposed solutions in terms of settling time, output current drivability and output power density for voltages slightly higher (450 mV) than the MOS threshold voltage.File | Dimensione | Formato | |
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