In this paper, we present a fully integrated dual dimensional reconfigurable charge pump (DDR-CP) for energy harvesting (EH) applications. EH systems often encounter significant input voltage variations due to changing environmental conditions, posing a challenge for conventional CPs, which are efficient only at discrete input-to-output voltage ratios. This limitation restricts their performance and efficiency over a wide power dynamic range (PDR). To address this, the proposed DDR-CP incorporates a dual-dimensional reconfiguration approach, optimizing operating frequency and CP stage configuration to maximize system efficiency across varying input and load conditions. A novel frequency tuning mechanism, termed dynamic source feed, is devised. Also, a mathematical analysis of dominant power losses over a wide PDR is derived, providing a robust design guideline for CP optimization. Fabricated in a 65-nm CMOS process, our DDR-CP integrates a total on-chip pumping capacitor of 176 pF within a compact active area of 0.286 mm2. The DDR-CP supports tri-mode operation, handling input voltages from 0.21 V to 0.7 V, and delivers up to 0 μW of output power. Measurement results demonstrate a peak PCE of 73% and an average PCE ranging from 30% to 70% across the entire input range, validated under a 55-KΩ output load.
Ultra-Low-VIN Dual-Dimensional Reconfigurable Charge Pump With Enhanced Power Conversion Efficiency and Extended Power Dynamic Range for Micro-Energy Harvesting Applications
Andrea Ballo;
2025-01-01
Abstract
In this paper, we present a fully integrated dual dimensional reconfigurable charge pump (DDR-CP) for energy harvesting (EH) applications. EH systems often encounter significant input voltage variations due to changing environmental conditions, posing a challenge for conventional CPs, which are efficient only at discrete input-to-output voltage ratios. This limitation restricts their performance and efficiency over a wide power dynamic range (PDR). To address this, the proposed DDR-CP incorporates a dual-dimensional reconfiguration approach, optimizing operating frequency and CP stage configuration to maximize system efficiency across varying input and load conditions. A novel frequency tuning mechanism, termed dynamic source feed, is devised. Also, a mathematical analysis of dominant power losses over a wide PDR is derived, providing a robust design guideline for CP optimization. Fabricated in a 65-nm CMOS process, our DDR-CP integrates a total on-chip pumping capacitor of 176 pF within a compact active area of 0.286 mm2. The DDR-CP supports tri-mode operation, handling input voltages from 0.21 V to 0.7 V, and delivers up to 0 μW of output power. Measurement results demonstrate a peak PCE of 73% and an average PCE ranging from 30% to 70% across the entire input range, validated under a 55-KΩ output load.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.