Electrical Wafer Sorting: a Deep Learning Approach for Advanced Wafer Defect Map Evaluation

In semiconductor environment, the manufacturing process and the related quality control hold a fundamental position. This aspect has been enhanced with the introduction of new materials, such as Silicon Carbide (SiC), and the necessity to perform a reliable method to detect wafer defects. In this paper, the Electrical Wafer Sorting (EWS), a reliable technique for creating electrical wafer maps, is combined with a deep learning pipeline to improve the defects identification. With respect to the state of the art, the innovative aspect is in the combination of a supervised system with an unsupervised sub-system. Compared to benchmarking algorithms present in literature, this approach allows to correctly classify well-know defect patterns and to characterize new defect morphology, leading to the identification of new potential issues in the production line and, overall, to a production yield improvement.