Simple Keeper Strategies for Domino Logic Gates

This paper, after an overview of most of the improved Domino Logic topologies with keeper, provides an in-depth and comprehensive comparison of the simplest keeper architectures: the Delayed Keeper, the Conditional Keeper, the Split Keeper and their combined variants. A design strategy for setting the keeper aspect ratio to satisfy a target noise immunity requirement is presented in the paper. All the considered topologies are then evaluated through extensive Monte Carlo simulations, assessing delay and its standard deviation, power consumption and Power-Delay-Product, as well as noise immunity and sensitivity to layout-dependent parasitics, implementing a wide set of logic gates in a 28 nm CMOS technology. A further comparison of the topologies, when the gates are cascaded to realize a simple Datapath, suggests that the Split Keeper, while being the simplest topology, generally provides a very favorable speed-power trade-off. In particular, although the speed advantage with respect to the more complex Delayed topologies is marginal, it generally results in less than half the power consumption and PDP.