This paper presents a fully integrated dual-loss-optimized reconfigurable charge pump for ultra-low-power energy harvesting applications. Conventional charge pumps typically optimize either the conduction loss or switching loss, leading to degradation of efficiency outside the narrow operating region. To overcome this limitation, the proposed architecture jointly optimizes both loss mechanisms through three synergistic circuit techniques. Firstly, a capacitor-free dynamic PMOS array ring oscillator adaptively scales the switching frequency to suppress unnecessary switching loss. Secondly, an adaptive pathway selection charge pump dynamically modulates the effective transistor widths to maintain efficient charge transfer from subthreshold to above-threshold operation. Thirdly, a compact successive-stage NMOS gate booster micro-cell achieves local enhancement of the gate-to-source drive of the NMOS charge transfer switches to reduce the conduction loss at low input voltages. Collectively, these techniques mitigate the dominant loss mechanism across different operating regimes, thereby enabling efficient operation over an extended power dynamic range. Fabricated in a 65-nm CMOS process, the prototype occupies an area of 359\times 809~\mu m with a total on-chip capacitance of 313 pF, including the pumping, boosting, and load capacitors. Measurement results demonstrate a peak power conversion efficiency of 67.59% at a minimum input voltage of 180 mV under a load of 800 k \Omega. Finally, the proposed charge pump provides a highly efficient and compact power management solution, well-suited for autonomous and self-sustained operation in micro-energy harvesting applications.

A 65-nm Fully Integrated Reconfigurable Charge Pump With Joint Optimization of Conduction and Switching Losses for Micro-Energy Harvesting Applications

Andrea Ballo;
2026-01-01

Abstract

This paper presents a fully integrated dual-loss-optimized reconfigurable charge pump for ultra-low-power energy harvesting applications. Conventional charge pumps typically optimize either the conduction loss or switching loss, leading to degradation of efficiency outside the narrow operating region. To overcome this limitation, the proposed architecture jointly optimizes both loss mechanisms through three synergistic circuit techniques. Firstly, a capacitor-free dynamic PMOS array ring oscillator adaptively scales the switching frequency to suppress unnecessary switching loss. Secondly, an adaptive pathway selection charge pump dynamically modulates the effective transistor widths to maintain efficient charge transfer from subthreshold to above-threshold operation. Thirdly, a compact successive-stage NMOS gate booster micro-cell achieves local enhancement of the gate-to-source drive of the NMOS charge transfer switches to reduce the conduction loss at low input voltages. Collectively, these techniques mitigate the dominant loss mechanism across different operating regimes, thereby enabling efficient operation over an extended power dynamic range. Fabricated in a 65-nm CMOS process, the prototype occupies an area of 359\times 809~\mu m with a total on-chip capacitance of 313 pF, including the pumping, boosting, and load capacitors. Measurement results demonstrate a peak power conversion efficiency of 67.59% at a minimum input voltage of 180 mV under a load of 800 k \Omega. Finally, the proposed charge pump provides a highly efficient and compact power management solution, well-suited for autonomous and self-sustained operation in micro-energy harvesting applications.
2026
CMOS charge pump
dual-loss-optimized reconfigurable charge pump
dynamic PMOS array
energy harvesting
power conversion efficiency
power dynamic range
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11769/722932
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