A 1.4 nm/s2/√Hz Real-Time Digital Signal Processing Chain on Artix-7 FPGA for Monolithic Sub-0.1 Hz Aerospace Accelerometers

Aerospace nano-gravimetry requires ultra-low-noise readout electronics to extract weak sub-Hz accelerations. Fully integrated monolithic complementary metal-oxide-semiconductor (CMOS) systems require frequency upconversion to bypass severe 1/f noise, alongside highly accurate digital downconversion. This letter presents a real-time digital signal processing (DSP) chain interfacing directly with a custom-fabricated 28-nm CMOS analog front-end. Deployed on an Artix-7 field programmable gate array, the DSP processes a 10 MSample/s serial stream from an on-chip 10-bit analog-to-digital converter. The architecture features a cross-correlation demodulator, a two-stage cascaded integrator-comb filter, and two 64-tap finite impulse response filters for anti-aliasing and suppressing high-power out-of-band interferers (up to 100μm/s2). Achieving a 106 decimation factor and 19-bit effective number of bits, measurements validate subleast significant bit signal recovery via thermal noise dithering. The system reconstructs 10nm/s2 accelerations at 0.1 Hz while fully preserving the application-specific integrated circuit. 1.4nm/s2/√Hz analog noise floor.