Approximate Wireless Networks-on-Chip

Thanks to the forgiving nature of the emerging recognition, mining and synthesis applications, approximate computing (AC) has been recently rediscovered as a viable technique for improving the performance of computing systems. Although the application of AC techniques has, in several cases, an indirect positive effect on the performance of the on-chip communication sub-system, there are only few works aimed at proposing AC techniques specifically designed to improve the efficiency of the on-chip communication fabric. This paper introduces the concept of approximate communication in the context of wireless network-on-chip (WiNoC) architectures. This paper presents a technique through which the programmer can annotate those data structures of an application that, whenever affected by errors, do not impact the functionality of the application itself but only the quality of its outputs. Based on this annotation, the communications induced by the access to such data structures are realized with a reduced energy effort that, however, results to an increase of the probability for the data to be affected by errors. The underlying hardware mechanisms enabling the energy versus reliability trade-off are based on the dynamic link voltage swing and on the dynamic transmitting power tuning of the wired links and wireless transmissions, respectively. Both the hardware and software components needed for supporting the proposed technique are presented. The technique is assessed on a set of representative benchmarks and the energy saving vs. application output quality is discussed.