One of the most promising architectures for performing deep neural network inferences on resource-constrained embedded devices is based on massive parallel and specialized cores interconnected by means of a Network-on-Chip (NoC). In this paper, we extensively evaluate NoC-based deep neural network accelerators by exploring the design space spanned by several architectural parameters. We show how latency is mainly dominated by the on-chip communication whereas energy consumption is mainly accounted by memory (both on-chip and off-chip).

Analyzing networks-on-chip based deep neural networks

Ascia G.;Catania V.;Monteleone S.;Palesi M.;Patti D.;
2019

Abstract

One of the most promising architectures for performing deep neural network inferences on resource-constrained embedded devices is based on massive parallel and specialized cores interconnected by means of a Network-on-Chip (NoC). In this paper, we extensively evaluate NoC-based deep neural network accelerators by exploring the design space spanned by several architectural parameters. We show how latency is mainly dominated by the on-chip communication whereas energy consumption is mainly accounted by memory (both on-chip and off-chip).
9781450367004
Deep Neural Network; Design space exploration; Network-on-Chip; Performance and energy evaluation
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/20.500.11769/382964
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