This paper presents Hybrid Cascode Compensation with Hybrid Q–Factor Control (HCCHQ), for three-stage feedback operational transconductance amplifiers (OTA) capable of handling any load capacitor (CL). The design incorporates an enhanced Miller compensation strategy, exploiting cascode-Miller compensation with hybrid pathways to effectively separate the dominant pole from non-dominant poles for bandwidth expansion. It also combines a hybrid quality factor (Q–factor) control with a local impedance attenuation (LIA) module, adjusting the Q–factor of non-dominant poles by mitigating the ringing in the time response and the frequency peaking for lighter CLs. The new design can accommodate capacitive loads ranging from zero to infinity, owing to the Miller– and load–compensated solutions for the light and heavy CLs, respectively. Fabricated in a 180-nm standard CMOS process, a prototype of the proposed amplifier demonstrates a quiescent current of 25 μA under a 1.8 V single supply. It boasts a compact 0.0055 mm2 area and exhibits unconditional stability when configured as a voltage buffer driving any CL. With a mean DC gain of 115 dB, the average unit-gain frequency (UGF) is 2.30 MHz and 0.11 MHz for 0.1 and 47 nF external capacitive loads, respectively. The mean 1% settling time is measured as 2.41 μs and 40 μs for the same capacitive loads, respectively, when a 0.4 V pulse signal is applied to the input.

Hybrid Cascode Compensation with Hybrid Q-Factor Control for Three-Stage Unconditionally Stable Amplifiers

Grasso A. D.
2024-01-01

Abstract

This paper presents Hybrid Cascode Compensation with Hybrid Q–Factor Control (HCCHQ), for three-stage feedback operational transconductance amplifiers (OTA) capable of handling any load capacitor (CL). The design incorporates an enhanced Miller compensation strategy, exploiting cascode-Miller compensation with hybrid pathways to effectively separate the dominant pole from non-dominant poles for bandwidth expansion. It also combines a hybrid quality factor (Q–factor) control with a local impedance attenuation (LIA) module, adjusting the Q–factor of non-dominant poles by mitigating the ringing in the time response and the frequency peaking for lighter CLs. The new design can accommodate capacitive loads ranging from zero to infinity, owing to the Miller– and load–compensated solutions for the light and heavy CLs, respectively. Fabricated in a 180-nm standard CMOS process, a prototype of the proposed amplifier demonstrates a quiescent current of 25 μA under a 1.8 V single supply. It boasts a compact 0.0055 mm2 area and exhibits unconditional stability when configured as a voltage buffer driving any CL. With a mean DC gain of 115 dB, the average unit-gain frequency (UGF) is 2.30 MHz and 0.11 MHz for 0.1 and 47 nF external capacitive loads, respectively. The mean 1% settling time is measured as 2.41 μs and 40 μs for the same capacitive loads, respectively, when a 0.4 V pulse signal is applied to the input.
2024
Feedback
frequency compensation
Miller compensation
operational amplifier
settling time and stability
Transconductance
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11769/623249
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