The explosive growth of AI workloads elevates on-chip communication and heat dissipation to first-order constraints. This survey paper consolidates thermal-aware Network-on-Chip (NoC) design for AI computing across tools, algorithms, and applications. Concretely, we first assemble a reproducible toolchain that couples cycle-accurate NoC simulators with power/thermal solvers and machine-learning surrogates for fast temperature prediction. We then structure the design space along three design dimensions: sensing strategies, control methodologies, and thermal- and traffic-aware data delivery. Finally, we close the loop among traffic, power, and temperature via an integrated co-simulation workflow, providing practical guidelines for thermal-aware NoC-based AI accelerator designs. Unlike general DNN-accelerator surveys, this survey paper focuses on the thermal-NoC interplay under realistic AI workloads and provides an actionable, closed-loop methodology and tooling for scalable, verifiable evaluation. We conclude with open challenges, scalable yet faithful co-simulation, standardized traces/interfaces, packaging-aware models, and uncertainty-aware surrogates, to guide the path toward thermally resilient, high-throughput AI systems.

Thermal-Aware NoC for AI Computing: Tools, Algorithms, and Applications

Palesi M.;
2026-01-01

Abstract

The explosive growth of AI workloads elevates on-chip communication and heat dissipation to first-order constraints. This survey paper consolidates thermal-aware Network-on-Chip (NoC) design for AI computing across tools, algorithms, and applications. Concretely, we first assemble a reproducible toolchain that couples cycle-accurate NoC simulators with power/thermal solvers and machine-learning surrogates for fast temperature prediction. We then structure the design space along three design dimensions: sensing strategies, control methodologies, and thermal- and traffic-aware data delivery. Finally, we close the loop among traffic, power, and temperature via an integrated co-simulation workflow, providing practical guidelines for thermal-aware NoC-based AI accelerator designs. Unlike general DNN-accelerator surveys, this survey paper focuses on the thermal-NoC interplay under realistic AI workloads and provides an actionable, closed-loop methodology and tooling for scalable, verifiable evaluation. We conclude with open challenges, scalable yet faithful co-simulation, standardized traces/interfaces, packaging-aware models, and uncertainty-aware surrogates, to guide the path toward thermally resilient, high-throughput AI systems.
2026
AI accelerators
co-simulation
network-on-chip (NoC)
thermal-aware design
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/20.500.11769/717491
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