The paper addresses the problem of topological mapping of intellectual properties (IPs) on the tiles of a meshbased network on chip (NoC) architecture. The aim is to obtain the Pareto mappings that maximize performance and minimize the amount of power consumption. As the problem is an NP-hard one, we propose a heuristic technique based on evolutionary computing to obtain an optimal approximation of the Pareto-optimal front in an efficient and accurate way. At the same time, two of the most widely-known approaches to mapping in mesh-based NoC architectures are extended in order to explore the mapping space in a multi-criteria mode. The approaches are then evaluated and compared, in terms of both accuracy and efficiency, on a platform based on an event-driven trace-based simulator which makes it possible to take account of important dynamic effects that have a great impact on mapping. The evaluation performed on real applications (an MPEG-4 codec and a cellular phone application) confirms the efficiency, accuracy and scalability of the proposed approach.
|Titolo:||Mapping Cores on Network-on-Chip|
|Data di pubblicazione:||2005|
|Citazione:||Mapping Cores on Network-on-Chip / ASCIA G; CATANIA V; PALESI M. - In: INTERNATIONAL JOURNAL OF COMPUTATIONAL INTELLIGENCE RESEARCH. - ISSN 0973-1873. - 1:1-2(2005), pp. 109-126.|
|Appare nelle tipologie:||1.1 Articolo in rivista|