SAFER: Self-Attentive Feature Extraction and Reduction

Modern RISC-V automotive systems provide deep microarchitectural observability through Hardware Performance Counters (HPCs). However, leveraging this telemetry for real-time anomaly detection introduces a severe curse of dimensionality, as processing hundreds of raw metrics is computationally unviable for resource-constrained Electronic Control Units (ECUs). This paper presents SAFER (Self-Attentive Feature Extraction and Reduction), a novel multi-stage ensemble framework designed to autonomously distill optimal hardware metrics for safety-critical applications. By jointly combining a custom Attention-LSTM neural architecture with Permutation Importance (PI), Mutual Information (MI), and Bootstrap Stability (BS) analysis, SAFER isolates stable and highly discriminative fault signatures. Experimental evaluations on a RISC-V out-of-order processor running automotive benchmarks demonstrate that SAFER compresses an initial space of 1,450 raw hardware metrics into a robust subset of just 36 features, achieving a 97.4% dimensionality reduction, a global accuracy of 96.1%, and an Area Under the Curve (AUC) of 98.6% across diverse microarchitectural fault injection scenarios, surpassing the full-feature baseline by 3.1% in accuracy. SAFER effectively resolves the conflict between diagnostic observability and embedded memory constraints, enabling the deployment of advanced sequence-aware anomaly detection models in compliance with ISO 26262 requirements.