IRIS
ASCIA, Giuseppe
 Distribuzione geografica
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Continente #
NA - Nord America 5.066
EU - Europa 2.473
AS - Asia 2.459
AF - Africa 605
SA - Sud America 426
Continente sconosciuto - Info sul continente non disponibili 163
OC - Oceania 11
Totale 11.203
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Nazione #
US - Stati Uniti d'America 4.866
SG - Singapore 1.180
RU - Federazione Russa 766
CN - Cina 733
CI - Costa d'Avorio 415
IT - Italia 405
BR - Brasile 346
IE - Irlanda 345
UA - Ucraina 336
CA - Canada 164
VN - Vietnam 163
DE - Germania 146
FR - Francia 134
SN - Senegal 100
KR - Corea 94
GB - Regno Unito 71
IN - India 69
FI - Finlandia 60
SE - Svezia 60
BD - Bangladesh 56
NL - Olanda 39
NG - Nigeria 36
AR - Argentina 31
TR - Turchia 29
PL - Polonia 27
MX - Messico 21
IQ - Iraq 17
CO - Colombia 16
CZ - Repubblica Ceca 16
JP - Giappone 16
ES - Italia 14
PK - Pakistan 14
UZ - Uzbekistan 13
HK - Hong Kong 12
ZA - Sudafrica 12
AT - Austria 11
AU - Australia 11
EC - Ecuador 10
CH - Svizzera 9
JO - Giordania 8
LB - Libano 8
MA - Marocco 8
VE - Venezuela 8
EG - Egitto 7
SA - Arabia Saudita 7
BG - Bulgaria 6
ID - Indonesia 6
PY - Paraguay 6
TN - Tunisia 6
CL - Cile 5
DZ - Algeria 5
LT - Lituania 5
BJ - Benin 4
GR - Grecia 4
KZ - Kazakistan 4
MY - Malesia 4
PH - Filippine 4
JM - Giamaica 3
KE - Kenya 3
KG - Kirghizistan 3
OM - Oman 3
PS - Palestinian Territory 3
AE - Emirati Arabi Uniti 2
AO - Angola 2
AZ - Azerbaigian 2
BB - Barbados 2
BY - Bielorussia 2
DO - Repubblica Dominicana 2
ET - Etiopia 2
GA - Gabon 2
HN - Honduras 2
IR - Iran 2
LU - Lussemburgo 2
PE - Perù 2
QA - Qatar 2
SK - Slovacchia (Repubblica Slovacca) 2
AL - Albania 1
BE - Belgio 1
BF - Burkina Faso 1
BS - Bahamas 1
BW - Botswana 1
CR - Costa Rica 1
DK - Danimarca 1
DM - Dominica 1
EE - Estonia 1
EU - Europa 1
GY - Guiana 1
HR - Croazia 1
IL - Israele 1
IM - Isola di Man 1
IS - Islanda 1
KW - Kuwait 1
LV - Lettonia 1
MK - Macedonia 1
ML - Mali 1
MN - Mongolia 1
MT - Malta 1
NI - Nicaragua 1
PR - Porto Rico 1
PT - Portogallo 1
Totale 11.035
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Città #
Dallas 829
Santa Clara 682
Singapore 667
Abidjan 415
San Jose 402
Chandler 400
Dublin 345
Jacksonville 341
Moscow 308
Ashburn 293
Boardman 142
Hefei 136
Catania 124
Toronto 104
Grafing 103
Dakar 100
Lawrence 99
Cambridge 96
Lauterbourg 94
Seoul 94
Andover 93
Beijing 90
Nanjing 88
Chicago 86
Los Angeles 81
San Mateo 65
Des Moines 55
Ho Chi Minh City 54
Houston 48
Council Bluffs 46
Hanoi 46
Helsinki 45
Nanchang 43
New York 43
Buffalo 39
Wilmington 36
Shenyang 35
Hebei 33
Amsterdam 32
São Paulo 31
Civitanova Marche 30
Saint Petersburg 30
Rome 28
Lagos 25
Orem 25
Bengaluru 23
Ottawa 23
Changsha 22
The Dalles 22
Brooklyn 21
Tianjin 21
Columbus 19
San Francisco 19
Atlanta 18
Augusta 18
Montreal 18
Jiaxing 17
Phoenix 16
Warsaw 16
Rio de Janeiro 15
Tokyo 15
Denver 14
London 14
Nuremberg 13
Ankara 12
Da Nang 12
Seattle 12
Boston 11
Chennai 11
Belo Horizonte 10
Brno 10
Norwalk 10
Stockholm 10
Tremestieri Etneo 10
Washington 10
Hong Kong 9
Palermo 9
Poplar 9
Pune 9
Amman 8
Baghdad 8
Brasília 8
Charlotte 8
Edinburgh 8
Jinan 8
Milan 8
Reggio Calabria 8
Abuja 7
Frankfurt am Main 7
Lahore 7
Paris 7
Porto Alegre 7
Haiphong 6
Johannesburg 6
Redondo Beach 6
Turin 6
Bogotá 5
Caltagirone 5
Canberra 5
Curitiba 5
Totale 7.642
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Nome #
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip 156
Approximate Wireless Networks-on-Chip 156
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures 151
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms 151
Analyzing networks-on-chip based deep neural networks 144
A New Selection Policy for Adaptive Routing in Network on Chip 142
A genetic approach to bus encoding 141
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems 141
A closed loop power manager for transmission power control in wireless network-on-chip architectures 139
A closed loop control based power manager for WiNoC architectures 138
A Fuzzy Buffer management scheme for shared-memory ATM switches 137
A Fuzzy Buffer Management Scheme for ATM and IP Networks 137
Exploiting data resilience in wireless network-on-chip architectures 135
A Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems 134
Data Encoding Schemes in Networks on Chip 134
A Framework for a Parallel Architecture Dedicated to Soft Computing 134
Coupling routing algorithm and data encoding for low power Networks on Chip 133
A Framework for Design Space Exploration of Parameterized VLSI Systems 133
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures 132
Mapping Cores on Network-on-Chip 131
A HIGH LEVEL HARDWARE MODEL FOR A PARALLEL FUZZY PROCESSOR 131
Exploiting antenna directivity in wireless NoC architectures 128
A dedicated parallel processor for fuzzy computation 127
Making android apps data-leak-safe by data flow analysis and code injection 127
An Efficient Hierarchical Fuzzy Approach for System Level System-on-a-Chip Design 126
An Instruction-Level Power Analysis Model with Data Dependency 125
A general purpose processor oriented to fuzzy reasoning 125
A Novel Approach to Design Space Exploration of Parameterized SOCs 125
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design 123
Switching Activity Reduction in Embedded Systems: A Genetic Bus Encoding Approach 122
A fuzzy system index to preserve interpretability in deep tuning of fuzzy rule based classifiers 121
A High Performance Processor for Application Based on Fuzzy Logic 119
Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices 119
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems 116
A Data Dependent Approach to Instruction Level Power Estimation 114
Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators 112
An Efficient Fuzzy System for Traffic Management in High Speed Packet Switched Networks 112
DNN Model Compression for IoT Domain Specific Hardware Accelerators 112
MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping 111
A Very High Speed Parallel Architecture for Fuzzy Applications 111
A Parallel Architecture for Soft Computing 110
Combined Application of Approximate Computing Techniques in DNN Hardware Accelerators 106
Computational Intelligence to Speed-Up Multi-Objective Design Space Exploration of Embedded Systems 106
Fuzzy Decision Making in Embedded System Design 106
Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression 104
A Soft Computing Technique for Performance Enhancement in High Speed Shared-Memory Switches 103
LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation 102
Improving energy consumption of NoC based architectures through approximate communication 102
DNN Hardware Accelerator Selection for Feasible Deployment of MARL-Based MAC Protocols in Industrial IoT Networks 101
On-Chip Communication Energy Reduction through Reliability Aware Adaptive Voltage Swing Scaling 101
Efficient Design Space Exploration for Application Specific Systems-on-a-Chip 100
VLSI hardware architecture for complex fuzzy systems 100
A Parallel Processor Architecture for Real-Time Fuzzy Applications 100
A VLSI fuzzy expert system for real-time traffic control in ATM networks 98
Design and Performance Evaluation of a VLSI Parallel Fuzzy Processor 97
An evolutionary management scheme in high performance packet switches, 96
Rule-driven VLSI fuzzy processor 96
A VLSI PARALLEL ARCHITECTURE FOR FUZZY EXPERT-SYSTEMS 95
Memory-Aware DNN Algorithm-Hardware Mapping via Integer Linear Programming 94
Fuzzy Simulation to Speedup Computer Design 94
Runtime Online Links Voltage Scaling for Low Energy Networks on Chip 93
A study on evolutionary multi-objective optimization with fuzzy approximation for computational expensive problems 93
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip 93
A reconfigurable parallel architecture for a fuzzy processor 92
Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning 91
Design of a VLSI Fuzzy Processor for ATM Traffic Sources Management 91
An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs 91
AN EFFICIENT HARDWARE ARCHITECTURE TO SUPPORT COMPLEX FUZZY REASONING 90
Multi-objective mapping for mesh-based NoC architectures 90
Improving inference latency and energy of network-on-chip based convolutional neural networks through weights compression 90
Designing for Parallel Fuzzy Computing 88
Tuning methodologies for parameterized systems design 87
An adaptive output selection function based on a fuzzy rule base system for Network on Chip 87
Improving LSTM-based Indoor Positioning via Simulation-Augmented Geomagnetic Field Dataset 86
An Encoding Scheme to Reduce Power Consumption in Networks-on-Chip 86
EPIC-Explorer: A parameterized VLIW-based platform framework for design space exploration 85
An integrated Fuzzy-GA Approach for Buffer Management 85
An efficient buffer management scheme based on evolutionary computing 84
Hyperblock Formation: A Power/Energy Perspective for High Performance VLIW Architectures 84
An efficient buffer management policy based on an integrated Fuzzy-GA approach 83
A pipeline parallel architecture for a fuzzy inference processor 83
An Adaptive Fuzzy Threshold Scheme for High Performance Shared-Memory Switch 82
Power/Energy Perspective on Hyperblock Formation 82
Design of a priority queue manager for high-speed packet switches 82
Improving Wormhole Adaptive Routing in Networks on Chip 82
Exploring Design Space of VLIW Architectures 80
Multi-objective Genetic Approach for System-level Exploration in Parameterized Systems-on-a-chip 80
An evolutionary approach for Pareto-optimal configurations in SOC platforms 78
Design of a VLSI Hardware PET Decoder 78
A VLSI Processor dedicated to Fuzzy Systems 77
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks 77
Design issues of an asynchronous parallel fuzzy processor 76
Exploiting the Approximate Computing Paradigm with DNN Hardware Accelerators 76
Design Space Exploration Methodologies for IP-based System-on-a-chip 75
Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems 75
An efficient hardware architecture to support complex fuzzy reasoning 73
A reconfigurable parallel architecture for a fuzzy processor 73
NoC Links Energy Reduction through Link Voltage Scaling 72
An evolutionary approach for reducing the switching activity in address buses 71
Multi-Objective Optimization of a Prameterized VLIW Architecture 70
Totale 10.527
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Categoria #
all - tutte 37.235
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 37.235
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/2022713 0 103 34 5 99 1 105 21 82 5 22 236
2022/20231.241 114 61 18 86 111 201 3 274 296 21 36 20
2023/2024762 29 212 24 44 23 193 7 19 1 79 84 47
2024/20252.111 41 231 102 67 483 347 79 102 117 201 183 158
2025/20264.708 268 204 932 320 697 907 507 88 244 245 107 189
2026/2027153 94 59 0 0 0 0 0 0 0 0 0 0
Totale 11.203