IRIS
ASCIA, Giuseppe
 Distribuzione geografica
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Continente #
NA - Nord America 1.892
EU - Europa 1.307
AF - Africa 411
AS - Asia 337
OC - Oceania 11
SA - Sud America 3
Continente sconosciuto - Info sul continente non disponibili 1
Totale 3.962
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Nazione #
US - Stati Uniti d'America 1.766
IE - Irlanda 344
UA - Ucraina 330
CI - Costa d'Avorio 307
CN - Cina 295
IT - Italia 237
DE - Germania 132
CA - Canada 126
RU - Federazione Russa 99
SN - Senegal 99
FI - Finlandia 40
SE - Svezia 28
FR - Francia 27
GB - Regno Unito 21
AU - Australia 11
IN - India 11
CH - Svizzera 8
PL - Polonia 8
UZ - Uzbekistan 8
AT - Austria 7
SG - Singapore 7
NL - Olanda 5
TR - Turchia 4
BG - Bulgaria 3
CZ - Repubblica Ceca 3
GR - Grecia 3
JP - Giappone 3
ES - Italia 2
LB - Libano 2
LU - Lussemburgo 2
NG - Nigeria 2
PK - Pakistan 2
SK - Slovacchia (Repubblica Slovacca) 2
TN - Tunisia 2
AR - Argentina 1
BE - Belgio 1
CL - Cile 1
DK - Danimarca 1
EE - Estonia 1
EG - Egitto 1
EU - Europa 1
HK - Hong Kong 1
ID - Indonesia 1
IM - Isola di Man 1
IR - Iran 1
LT - Lituania 1
PE - Perù 1
PT - Portogallo 1
SA - Arabia Saudita 1
VN - Vietnam 1
Totale 3.962
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Città #
Chandler 400
Dublin 344
Jacksonville 340
Abidjan 307
Grafing 103
Dakar 99
Lawrence 99
Toronto 98
Cambridge 96
Andover 93
Ashburn 92
Nanjing 88
Catania 87
San Mateo 65
Des Moines 53
Nanchang 43
Boardman 40
Houston 39
Wilmington 36
Shenyang 35
Helsinki 34
Hebei 33
Saint Petersburg 30
Ottawa 23
Changsha 22
Tianjin 21
Rome 20
Augusta 17
Jiaxing 17
Nuremberg 12
Norwalk 10
Moscow 9
San Francisco 9
Washington 8
Jinan 7
Palermo 7
Pune 7
Los Angeles 6
Caltagirone 5
Canberra 5
Seattle 5
Spino D'adda 5
Vicenza 5
Acireale 4
Den Haag 4
Frankfurt Am Main 4
Hangzhou 4
Kunming 4
London 4
Melbourne 4
Montreal 4
Adrano 3
Ann Arbor 3
Beijing 3
Edinburgh 3
Faggiano 3
Lappeenranta 3
Princeton 3
Reggio Calabria 3
Rosolini 3
Abuja 2
Bratislava 2
Cergy 2
Frankfurt am Main 2
Hanover 2
Karachi 2
Ksar Hellal 2
Lanzhou 2
Lausanne 2
Liberty Lake 2
Luxembourg 2
Macerata Campania 2
Mascalucia 2
Mazara Del Vallo 2
Milan 2
Mountain View 2
New York 2
Ningbo 2
Paola 2
Patti 2
Singapore 2
Tokyo 2
Zhengzhou 2
Almere Stad 1
Belpasso 1
Brisbane 1
Brussels 1
Buenos Aires 1
Böblingen 1
Cairo 1
Central 1
Changchun 1
Charlotte 1
Douglas 1
Eichenau 1
Fuzhou 1
Guangzhou 1
Hanoi 1
Jinhua 1
Kiev 1
Totale 2.996
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Nome #
Exploiting data resilience in wireless network-on-chip architectures 84
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures 77
An Instruction-Level Power Analysis Model with Data Dependency 63
Coupling routing algorithm and data encoding for low power Networks on Chip 63
Switching Activity Reduction in Embedded Systems: A Genetic Bus Encoding Approach 62
Exploiting antenna directivity in wireless NoC architectures 57
A Parallel Processor Architecture for Real-Time Fuzzy Applications 57
A genetic approach to bus encoding 56
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems 53
Mapping Cores on Network-on-Chip 52
Efficient Design Space Exploration for Application Specific Systems-on-a-Chip 51
An Efficient Fuzzy System for Traffic Management in High Speed Packet Switched Networks 50
A closed loop power manager for transmission power control in wireless network-on-chip architectures 50
Computational Intelligence to Speed-Up Multi-Objective Design Space Exploration of Embedded Systems 50
Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices 50
Data Encoding Schemes in Networks on Chip 48
VLSI hardware architecture for complex fuzzy systems 48
An adaptive output selection function based on a fuzzy rule base system for Network on Chip 48
AN EFFICIENT HARDWARE ARCHITECTURE TO SUPPORT COMPLEX FUZZY REASONING 47
An Efficient Hierarchical Fuzzy Approach for System Level System-on-a-Chip Design 47
A New Selection Policy for Adaptive Routing in Network on Chip 47
A Soft Computing Technique for Performance Enhancement in High Speed Shared-Memory Switches 47
A reconfigurable parallel architecture for a fuzzy processor 47
MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping 46
Runtime Online Links Voltage Scaling for Low Energy Networks on Chip 46
A general purpose processor oriented to fuzzy reasoning 46
A HIGH LEVEL HARDWARE MODEL FOR A PARALLEL FUZZY PROCESSOR 46
Making android apps data-leak-safe by data flow analysis and code injection 46
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures 45
Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression 45
A VLSI PARALLEL ARCHITECTURE FOR FUZZY EXPERT-SYSTEMS 44
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems 44
Analyzing networks-on-chip based deep neural networks 44
On-Chip Communication Energy Reduction through Reliability Aware Adaptive Voltage Swing Scaling 43
Design of a VLSI Fuzzy Processor for ATM Traffic Sources Management 43
Fuzzy Decision Making in Embedded System Design 43
A dedicated parallel processor for fuzzy computation 43
A Framework for a Parallel Architecture Dedicated to Soft Computing 43
A Novel Approach to Design Space Exploration of Parameterized SOCs 43
An Encoding Scheme to Reduce Power Consumption in Networks-on-Chip 43
Rule-driven VLSI fuzzy processor 42
An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs 42
A VLSI fuzzy expert system for real-time traffic control in ATM networks 42
A closed loop control based power manager for WiNoC architectures 42
Approximate Wireless Networks-on-Chip 42
Multi-objective mapping for mesh-based NoC architectures 41
A Data Dependent Approach to Instruction Level Power Estimation 41
A fuzzy system index to preserve interpretability in deep tuning of fuzzy rule based classifiers 41
A High Performance Processor for Application Based on Fuzzy Logic 40
A Fuzzy Buffer management scheme for shared-memory ATM switches 40
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks 40
A Fuzzy Buffer Management Scheme for ATM and IP Networks 40
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms 40
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip 40
An evolutionary management scheme in high performance packet switches, 39
A pipeline parallel architecture for a fuzzy inference processor 39
Hyperblock Formation: A Power/Energy Perspective for High Performance VLIW Architectures 38
Design of a VLSI Hardware PET Decoder 38
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design 38
A Framework for Design Space Exploration of Parameterized VLSI Systems 38
An evolutionary approach for Pareto-optimal configurations in SOC platforms 37
Exploring Design Space of VLIW Architectures 37
An integrated Fuzzy-GA Approach for Buffer Management 37
Improving Wormhole Adaptive Routing in Networks on Chip 37
Tuning methodologies for parameterized systems design 36
An efficient buffer management scheme based on evolutionary computing 36
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip 36
Improving energy consumption of NoC based architectures through approximate communication 36
Designing for Parallel Fuzzy Computing 36
A study on evolutionary multi-objective optimization with fuzzy approximation for computational expensive problems 35
Design and Performance Evaluation of a VLSI Parallel Fuzzy Processor 35
Fuzzy Simulation to Speedup Computer Design 34
LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation 33
An efficient hardware architecture to support complex fuzzy reasoning 33
Improving inference latency and energy of network-on-chip based convolutional neural networks through weights compression 33
DNN Model Compression for IoT Domain Specific Hardware Accelerators 33
An evolutionary approach for reducing the switching activity in address buses 32
An Adaptive Fuzzy Threshold Scheme for High Performance Shared-Memory Switch 32
Power/Energy Perspective on Hyperblock Formation 32
An Evolutionary Approach to Network on Chip Mapping Problem 32
Design of a priority queue manager for high-speed packet switches 32
A Parallel Architecture for Soft Computing 32
Multi-objective Genetic Approach for System-level Exploration in Parameterized Systems-on-a-chip 32
Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators 31
EPIC-Explorer: A parameterized VLIW-based platform framework for design space exploration 31
Design issues of an asynchronous parallel fuzzy processor 31
Multi-Objective Optimization of a Prameterized VLIW Architecture 31
NoC Links Energy Reduction through Link Voltage Scaling 30
Low Energy Mapping Techniques under Reliability and Bandwidth Constraints 30
Design Space Exploration Methodologies for IP-based System-on-a-chip 30
A reconfigurable parallel architecture for a fuzzy processor 30
An efficient buffer management policy based on an integrated Fuzzy-GA approach 29
A Very High Speed Parallel Architecture for Fuzzy Applications 29
A VLSI Processor dedicated to Fuzzy Systems 27
An optimized parallel RISC processor for fuzzy computing 27
Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems 27
Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip 25
Parameterised System Design Based on Genetic Algorithms 24
Tuning methodologies for parameterized systems design 24
Design of a VLSI parallel processor for fuzzy computing 23
Totale 4.077
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Categoria #
all - tutte 12.259
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 12.259
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/20197 0 0 0 0 0 0 0 0 0 0 1 6
2019/2020546 211 41 39 4 47 4 25 5 68 6 65 31
2020/2021638 6 62 77 10 184 7 59 3 171 2 42 15
2021/2022808 95 103 34 5 99 1 105 21 82 5 22 236
2022/20231.241 114 61 18 86 111 201 3 274 296 21 36 20
2023/2024633 29 212 24 44 23 193 7 19 1 79 2 0
Totale 4.102