IRIS
ASCIA, Giuseppe
 Distribuzione geografica
Salva come PNG Salva come JPEG
Continente #
NA - Nord America 3.915
EU - Europa 1.515
AS - Asia 1.351
AF - Africa 543
SA - Sud America 289
OC - Oceania 11
Continente sconosciuto - Info sul continente non disponibili 1
Totale 7.625
Salva come PNG Salva come JPEG
Nazione #
US - Stati Uniti d'America 3.769
SG - Singapore 616
CN - Cina 540
CI - Costa d'Avorio 415
IT - Italia 346
IE - Irlanda 344
UA - Ucraina 332
BR - Brasile 264
DE - Germania 140
CA - Canada 135
RU - Federazione Russa 106
SN - Senegal 100
FI - Finlandia 60
GB - Regno Unito 46
IN - India 46
KR - Corea 40
SE - Svezia 32
FR - Francia 28
VN - Vietnam 20
BD - Bangladesh 17
TR - Turchia 17
CZ - Repubblica Ceca 16
AR - Argentina 12
PL - Polonia 12
AU - Australia 11
AT - Austria 10
JP - Giappone 10
UZ - Uzbekistan 10
CH - Svizzera 8
NL - Olanda 8
ES - Italia 7
IQ - Iraq 7
MA - Marocco 7
EG - Egitto 5
MX - Messico 5
BG - Bulgaria 4
CO - Colombia 4
HK - Hong Kong 4
JO - Giordania 4
PK - Pakistan 4
TN - Tunisia 4
DZ - Algeria 3
GR - Grecia 3
LB - Libano 3
ZA - Sudafrica 3
CL - Cile 2
HN - Honduras 2
ID - Indonesia 2
IR - Iran 2
KE - Kenya 2
LU - Lussemburgo 2
NG - Nigeria 2
PY - Paraguay 2
SA - Arabia Saudita 2
SK - Slovacchia (Repubblica Slovacca) 2
VE - Venezuela 2
AZ - Azerbaigian 1
BB - Barbados 1
BE - Belgio 1
BW - Botswana 1
BY - Bielorussia 1
DK - Danimarca 1
DO - Repubblica Dominicana 1
EC - Ecuador 1
EE - Estonia 1
ET - Etiopia 1
EU - Europa 1
GY - Guiana 1
IL - Israele 1
IM - Isola di Man 1
IS - Islanda 1
KG - Kirghizistan 1
KW - Kuwait 1
KZ - Kazakistan 1
LT - Lituania 1
MN - Mongolia 1
NI - Nicaragua 1
PE - Perù 1
PS - Palestinian Territory 1
PT - Portogallo 1
RS - Serbia 1
SV - El Salvador 1
Totale 7.625
Salva come PNG Salva come JPEG
Città #
Dallas 812
Santa Clara 655
Abidjan 415
Chandler 400
Singapore 375
Dublin 344
Jacksonville 340
Boardman 142
Catania 117
Ashburn 111
Grafing 103
Dakar 100
Lawrence 99
Toronto 99
Cambridge 96
Andover 93
Hefei 93
Nanjing 88
Chicago 78
San Mateo 65
Des Moines 53
Beijing 49
Helsinki 45
Nanchang 43
Seoul 40
Houston 39
Council Bluffs 37
Wilmington 36
Shenyang 35
Hebei 33
Civitanova Marche 30
Saint Petersburg 30
São Paulo 24
Los Angeles 23
Ottawa 23
Bengaluru 22
Changsha 22
The Dalles 22
Tianjin 21
Rome 20
Columbus 19
Augusta 17
Jiaxing 17
San Francisco 17
Brooklyn 14
Nuremberg 12
Rio de Janeiro 11
Brno 10
Moscow 10
Norwalk 10
Washington 10
New York 9
Palermo 9
Pune 9
Tokyo 9
Belo Horizonte 8
Edinburgh 8
Jinan 8
Seattle 8
Tremestieri Etneo 8
Ho Chi Minh City 7
London 7
Reggio Calabria 7
Ankara 6
Boston 6
Hanoi 6
Montreal 6
Phoenix 6
Baghdad 5
Caltagirone 5
Canberra 5
Espoo 5
Spino D'adda 5
Turin 5
Vicenza 5
Acireale 4
Amman 4
Atlanta 4
Curitiba 4
Den Haag 4
Frankfurt Am Main 4
Hangzhou 4
Kunming 4
Lappeenranta 4
Melbourne 4
Milan 4
Mumbai 4
Munich 4
Porto Alegre 4
Sorocaba 4
Stockholm 4
Warsaw 4
Adrano 3
Ann Arbor 3
Brasília 3
Campinas 3
Casablanca 3
Charlotte 3
Contagem 3
Faggiano 3
Totale 5.673
Salva come PNG Salva come JPEG
Nome #
Exploiting data resilience in wireless network-on-chip architectures 114
Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures 109
Approximate Wireless Networks-on-Chip 107
Mapping Cores on Network-on-Chip 106
Coupling routing algorithm and data encoding for low power Networks on Chip 106
A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures 103
Switching Activity Reduction in Embedded Systems: A Genetic Bus Encoding Approach 100
A closed loop power manager for transmission power control in wireless network-on-chip architectures 100
A genetic approach to bus encoding 100
Exploiting antenna directivity in wireless NoC architectures 99
An Instruction-Level Power Analysis Model with Data Dependency 98
A GA Based Design Space Exploration Framework for Parameterized System-on-a-Chip Platforms 96
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems 94
A closed loop control based power manager for WiNoC architectures 94
Data Encoding Schemes in Networks on Chip 92
A New Selection Policy for Adaptive Routing in Network on Chip 91
Analyzing networks-on-chip based deep neural networks 91
A Framework for a Parallel Architecture Dedicated to Soft Computing 90
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip 90
Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices 90
An Efficient Fuzzy System for Traffic Management in High Speed Packet Switched Networks 89
A HIGH LEVEL HARDWARE MODEL FOR A PARALLEL FUZZY PROCESSOR 89
A Fuzzy Buffer management scheme for shared-memory ATM switches 89
A dedicated parallel processor for fuzzy computation 88
A Fuzzy Buffer Management Scheme for ATM and IP Networks 86
A Framework for Design Space Exploration of Parameterized VLSI Systems 85
An Efficient Hierarchical Fuzzy Approach for System Level System-on-a-Chip Design 84
A High Performance Processor for Application Based on Fuzzy Logic 84
MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping 83
LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation 82
A general purpose processor oriented to fuzzy reasoning 82
A Novel Approach to Design Space Exploration of Parameterized SOCs 82
Computational Intelligence to Speed-Up Multi-Objective Design Space Exploration of Embedded Systems 81
A Data Dependent Approach to Instruction Level Power Estimation 81
A fuzzy system index to preserve interpretability in deep tuning of fuzzy rule based classifiers 81
Making android apps data-leak-safe by data flow analysis and code injection 81
Fuzzy Decision Making in Embedded System Design 80
A Parallel Processor Architecture for Real-Time Fuzzy Applications 79
A Soft Computing Technique for Performance Enhancement in High Speed Shared-Memory Switches 79
Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators 78
Efficient Design Space Exploration for Application Specific Systems-on-a-Chip 78
On-Chip Communication Energy Reduction through Reliability Aware Adaptive Voltage Swing Scaling 78
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems 78
VLSI hardware architecture for complex fuzzy systems 77
A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design 77
Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression 76
A VLSI PARALLEL ARCHITECTURE FOR FUZZY EXPERT-SYSTEMS 75
Improving energy consumption of NoC based architectures through approximate communication 75
DNN Model Compression for IoT Domain Specific Hardware Accelerators 75
An evolutionary management scheme in high performance packet switches, 74
Rule-driven VLSI fuzzy processor 72
A VLSI fuzzy expert system for real-time traffic control in ATM networks 71
AN EFFICIENT HARDWARE ARCHITECTURE TO SUPPORT COMPLEX FUZZY REASONING 70
Design of a VLSI Fuzzy Processor for ATM Traffic Sources Management 70
Runtime Online Links Voltage Scaling for Low Energy Networks on Chip 69
A Parallel Architecture for Soft Computing 69
A reconfigurable parallel architecture for a fuzzy processor 69
Improving inference latency and energy of network-on-chip based convolutional neural networks through weights compression 69
An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs 68
A Very High Speed Parallel Architecture for Fuzzy Applications 68
Multi-objective mapping for mesh-based NoC architectures 67
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip 67
Fuzzy Simulation to Speedup Computer Design 67
An adaptive output selection function based on a fuzzy rule base system for Network on Chip 66
Design and Performance Evaluation of a VLSI Parallel Fuzzy Processor 65
An Encoding Scheme to Reduce Power Consumption in Networks-on-Chip 65
An integrated Fuzzy-GA Approach for Buffer Management 65
An efficient buffer management scheme based on evolutionary computing 64
Tuning methodologies for parameterized systems design 63
Hyperblock Formation: A Power/Energy Perspective for High Performance VLIW Architectures 63
Exploring Design Space of VLIW Architectures 63
EPIC-Explorer: A parameterized VLIW-based platform framework for design space exploration 62
A pipeline parallel architecture for a fuzzy inference processor 62
Multi-objective Genetic Approach for System-level Exploration in Parameterized Systems-on-a-chip 62
Designing for Parallel Fuzzy Computing 62
An evolutionary approach for Pareto-optimal configurations in SOC platforms 61
An Adaptive Fuzzy Threshold Scheme for High Performance Shared-Memory Switch 61
Design of a VLSI Hardware PET Decoder 61
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks 61
DNN Hardware Accelerator Selection for Feasible Deployment of MARL-Based MAC Protocols in Industrial IoT Networks 60
Combined Application of Approximate Computing Techniques in DNN Hardware Accelerators 60
An efficient buffer management policy based on an integrated Fuzzy-GA approach 60
Design of a priority queue manager for high-speed packet switches 60
Improving Wormhole Adaptive Routing in Networks on Chip 60
A study on evolutionary multi-objective optimization with fuzzy approximation for computational expensive problems 57
A Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems 56
Power/Energy Perspective on Hyperblock Formation 56
Design Space Exploration Methodologies for IP-based System-on-a-chip 56
Design issues of an asynchronous parallel fuzzy processor 55
A VLSI Processor dedicated to Fuzzy Systems 55
An Evolutionary Approach to Network on Chip Mapping Problem 55
An efficient hardware architecture to support complex fuzzy reasoning 55
Multi-Objective Optimization of a Prameterized VLIW Architecture 55
A reconfigurable parallel architecture for a fuzzy processor 54
Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems 54
NoC Links Energy Reduction through Link Voltage Scaling 51
An evolutionary approach for reducing the switching activity in address buses 50
An optimized parallel RISC processor for fuzzy computing 50
Low Energy Mapping Techniques under Reliability and Bandwidth Constraints 49
Parameterised System Design Based on Genetic Algorithms 48
Totale 7.454
Salva come PNG Salva come JPEG
Categoria #
all - tutte 27.009
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 27.009
Salva come PNG Salva come JPEG


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021493 0 0 0 10 184 7 59 3 171 2 42 15
2021/2022808 95 103 34 5 99 1 105 21 82 5 22 236
2022/20231.241 114 61 18 86 111 201 3 274 296 21 36 20
2023/2024762 29 212 24 44 23 193 7 19 1 79 84 47
2024/20252.111 41 231 102 67 483 347 79 102 117 201 183 158
2025/20261.430 268 204 932 26 0 0 0 0 0 0 0 0
Totale 7.772