IRIS
PALUMBO, Gaetano
 Distribuzione geografica
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Continente #
NA - Nord America 21.435
AS - Asia 7.355
EU - Europa 6.276
SA - Sud America 1.476
AF - Africa 961
OC - Oceania 58
Continente sconosciuto - Info sul continente non disponibili 16
AN - Antartide 2
Totale 37.579
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Nazione #
US - Stati Uniti d'America 20.800
SG - Singapore 3.698
CN - Cina 2.517
IE - Irlanda 1.632
UA - Ucraina 1.448
IT - Italia 1.364
BR - Brasile 1.271
CI - Costa d'Avorio 653
CA - Canada 565
VN - Vietnam 404
RU - Federazione Russa 402
FI - Finlandia 292
SE - Svezia 235
DE - Germania 213
SN - Senegal 189
FR - Francia 169
GB - Regno Unito 156
KR - Corea 153
IN - India 132
AR - Argentina 76
HK - Hong Kong 74
CH - Svizzera 71
NL - Olanda 71
PL - Polonia 46
AU - Australia 45
UZ - Uzbekistan 43
BD - Bangladesh 42
JP - Giappone 42
AT - Austria 41
MX - Messico 41
ZA - Sudafrica 36
EC - Ecuador 35
TW - Taiwan 33
IQ - Iraq 32
CZ - Repubblica Ceca 29
TR - Turchia 28
ID - Indonesia 26
CO - Colombia 25
GR - Grecia 22
LB - Libano 20
PK - Pakistan 20
PE - Perù 17
EG - Egitto 16
ES - Italia 16
BJ - Benin 15
EU - Europa 15
NG - Nigeria 15
PY - Paraguay 15
VE - Venezuela 13
CL - Cile 12
NZ - Nuova Zelanda 12
AE - Emirati Arabi Uniti 11
IR - Iran 11
KE - Kenya 11
PH - Filippine 11
IL - Israele 10
BG - Bulgaria 9
MA - Marocco 9
PT - Portogallo 9
SA - Arabia Saudita 9
BE - Belgio 7
JO - Giordania 7
TN - Tunisia 7
BY - Bielorussia 6
DK - Danimarca 6
DZ - Algeria 6
JM - Giamaica 6
OM - Oman 6
RS - Serbia 6
UY - Uruguay 6
HN - Honduras 5
LT - Lituania 5
BO - Bolivia 4
KZ - Kazakistan 4
PA - Panama 4
AL - Albania 3
AZ - Azerbaigian 3
BN - Brunei Darussalam 3
NO - Norvegia 3
SV - El Salvador 3
CR - Costa Rica 2
DO - Repubblica Dominicana 2
GY - Guiana 2
HR - Croazia 2
HU - Ungheria 2
KG - Kirghizistan 2
LU - Lussemburgo 2
ML - Mali 2
MY - Malesia 2
NP - Nepal 2
PS - Palestinian Territory 2
RO - Romania 2
TH - Thailandia 2
TL - Timor Orientale 2
TT - Trinidad e Tobago 2
AQ - Antartide 1
BA - Bosnia-Erzegovina 1
BH - Bahrain 1
BS - Bahamas 1
CU - Cuba 1
Totale 37.562
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Città #
Dallas 9.393
Santa Clara 2.197
Singapore 1.716
Dublin 1.618
Jacksonville 1.534
Chandler 1.298
Abidjan 653
Boardman 638
Nanjing 515
Cambridge 447
Lawrence 447
Ashburn 442
Andover 436
Hefei 416
Toronto 415
Civitanova Marche 393
Catania 321
Beijing 311
Helsinki 280
Los Angeles 279
San Mateo 219
Des Moines 214
Chicago 200
Wilmington 195
Dakar 189
Houston 179
Dong Ket 178
Seoul 147
Nanchang 145
Shenyang 142
Hebei 123
São Paulo 114
Saint Petersburg 111
Changsha 103
Jiaxing 97
Ottawa 92
Ho Chi Minh City 90
Tianjin 90
Buffalo 83
Council Bluffs 78
Grafing 61
Milan 60
The Dalles 58
Hong Kong 57
Columbus 56
Rio de Janeiro 47
New York 46
Palermo 46
Hanoi 45
Belo Horizonte 39
Moscow 39
Jinan 38
Seattle 37
Redondo Beach 36
Amsterdam 34
Munich 31
Hangzhou 29
Nuremberg 29
Washington 29
Brasília 27
Norwalk 27
Tremestieri Etneo 26
Pune 25
Chennai 24
Liberty Lake 24
Piedimonte Etneo 24
Rome 24
Tokyo 23
Brno 22
Montreal 21
Phoenix 21
Warsaw 21
Zhengzhou 21
Brooklyn 19
Taizhou 19
Duncan 18
Naples 18
Boston 17
Curitiba 17
Kunming 17
London 17
Ningbo 17
New Taipei City 16
Porto Alegre 16
Tashkent 16
Ann Arbor 15
Cotonou 15
Lima 15
Bengaluru 14
Campinas 14
Den Haag 14
Johannesburg 14
San Jose 14
Stockholm 14
Acireale 13
Frankfurt Am Main 13
Guayaquil 13
Haiphong 13
Juiz de Fora 13
Mumbai 13
Totale 28.099
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Nome #
A 0.003-mm2 50-mW Three-Stage Amplifier Driving 10-nF with 2.7-MHz GBW 3.631
0.5-v frequency dividers in folded mcml exploiting forward body bias: Analysis and comparison 3.495
Mixed Full Adder topologies for high-performance low-power arithmetic circuits 222
A 1-V CMOS Output Stage with High Linearity 165
A Bulk Current Regulation Technique for Dual-Branch Cross-Coupled Charge Pumps 159
1.5-V CMOS CCII+ WITH HIGH CURRENT-DRIVING CAPABILITY 152
Design guidelines of CMOS class-AB output stages: a tutorial 148
1.2-V CMOS op-amp with a dynamically biased output stage 147
A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers 141
A 1.5-V high drive capability CMOS op-amp 140
1.5V power supply CMOS voltage squarer 139
1.2-V CMOS OUTPUT STAGE WITH IMPROVED DRIVE CAPABILITY 138
1.5-V High-Drive Second Generation Current Conveyor 135
A Clock Boosted Charge Pump with Reduced Rise Time 135
A CMOS CURRENT AMPLIFIER 129
A 1.5 CMOS Voltage Multiplier 129
195-nW 120-dB Subthreshold CMOS OTA Driving up to 200 pF and Occupying only 4.4·10-3 mm2 120
A 50-mA 1-nF Low-Voltage Low-Dropout Voltage Regulator for SoC Applications 120
A 1.35-V Sense Amplifier for Non Volatile Memories based on Current Mode Approach 119
A New Method for Harmonic Distortion Analysis in Class-AB Stages 118
1V CMOS output stage with excellent linearity 115
Dynamic-biased capacitor-free NMOS LDO voltage regulator 114
2-MHz GBW CMOS OTA for 250 pF to 1.25 nF capacitive load 114
Robust design of CMOS amplifiers oriented to settling-time specification 113
A Charge Loss Aware Advanced Model of Dickson Voltage Multipliers 112
PERFORMANCE EVALUATION OF ADIABATIC GATES 112
Design of low-power high-speed bipolar frequency dividers 112
Signal Amplifiers 110
Advances in Reversed Nested Miller Compensation 110
Autonomous Energy-Efficient Wireless Sensor Network Platform for Home/Office Automation 109
Design of an Nth order Dickson voltage multiplier 106
Optimized Design of an N-th Order Dickson Voltage Multiplier 105
A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads 105
An Accurate Ultra-Compact I–V Model for Nanometer MOS Transistors With Applications on Digital Circuits 104
A Schmitt trigger by means of CCII+ 103
Optimized Charge Pump with Clock Booster for Reduced Rise Time or Silicon Area 103
Approach to the design of low-voltage SC filters 102
Area-efficient design of three- and four-stage voltage multipliers for power integrated circuits 102
Variations in Nanometer CMOS Flip-Flops: Part I – Timing and Impact of Process Variations 101
Integrated Quenching-and-Reset Circuit for Single-Photon Avalanche Diodes 100
A New Advanced RNMC Technique with Dual-Active Current and Voltage Buffers for Low-Power High-Load Three-Stage Amplifiers 100
A New Accurate Analytical Expression for the SiPM Transient Response to Single Photons 100
Analysis and optimization of a novel CMOS multiplier 99
Class-AB CMOS output stages suitable for low-voltage amplifiers in nanometer technologies 99
Pseudo-Random Sequence Generators with Improved Inviolability Performance 98
Introduzione ai Dispositivi Elettronici 97
A New Enhanced PSPICE Implementation of the Equivalent Circuit Model of SiPM Detectors 96
"Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems" (di Keh-La Lin, A. Kemna, B. Hosticka), in IEEE Circuits & Devices Magazine 95
Design procedures for three-stage CMOS OTAs with nested-Miller compensation 95
An approach to test the open-loop parameters of feedback amplifiers 95
DESIGN METHODOLOGY AND ADVANCES IN NESTED-MILLER COMPENSATION 94
Introduzione ai Convertitori A/D del tipo Sigma-Delta 93
IMPROVED BEHAVIORAL AND DESIGN MODEL OF AN N-TH ORDER CHARGE PUMP 92
CML RING OSCILLATORS: OSCILLATION FREQUENCY 92
AN ACCURATE OFFSET–COMPENSATED CURRENT COMPARATOR 92
Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time 91
The noise performance of Miller CMOS operational amplifiers with current-buffer frequency compensation 90
Switched capacitor compatible minimum-maximum function 90
A compensation strategy for two-stage CMOS opamps based on current buffer 90
An Efficient RNM Compensation Topology with Voltage Buffer and Nulling Resistors for Large-Capacitive-Load Three-Stage OTAs 90
Single-miller all-passive compensation network for three-stage OTAs 90
NEW CMOS CURRENT MIRRORS WITH IMPROVED HIGH-FREQUENCY RESPONSE 89
Robust Miller Compensation With Current Amplifiers Applied to LDO Voltage Regulator 89
CMOS CURRENT AMPLIFIERS 89
DOUBLE AND TRIPLE CHARGE PUMPS WITH MOS DIODES - DYNAMIC-MODELS TO AN OPTIMIZED DESIGN 89
Three-stage single-miller CMOS OTA driving 10 nF with 1.46-MHz GBW 89
Memorie Ferroelettriche 88
AN OPTIMIZED COMPENSATION STRATEGY FOR 2-STAGE CMOS OP AMPS 88
Behavioral modeling of statistical phenomena of single-photon avalanche diodes 88
Design and Comparison of Very Low-Voltage CMOS Output Stages 88
GAIN-COMPENSATED SAMPLE-AND-HOLD CIRCUIT FOR HIGH-FREQUENCY APPLICATION 88
A Novel Low-Power High-Speed Rail-to-Rail Class-B Buffer Amplifier for LCD Output Drivers 88
A Fuzzy A/D Converter by Means of Current-Mode Approach 88
Analytical Figure of Merit Evaluation of RNMC Networks for Low-Power Three-Stage OTAs 88
HIGH LINEARITY CMOS CURRENT OUTPUT STAGE 87
Improved Power-Efficient RNMC Technique with Voltage Buffer and Nulling Resistors for Low-Power High-Load Three-Stage Amplifiers 87
MODELING OF SOURCE COUPLED LOGIC GATES 86
Guest editorial 86
Analytical Comparison of Frequency Compensation Techniques in Three-Stage Amplifiers 86
Power Supply Rejection of Widlar Bandgap Voltage Reference 86
A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETs 86
A Fuzzy Controller for Step-Up DC/DC Converters 86
Resistance of Feedback Amplifiers: A Novel Representation 85
Improved Low-Power High-Speed Buffer Amplifier with Slew-Rate Enhancement for LCD Applications 85
Solutions for CMOS Current Amplifiers with High-Drive Output Stage 85
An Approach to the Design of Low-Voltage SC Filters 85
Charge Pumps for Ultra-Low-Power Applications: Analysis, Design and New Solutions 85
Distortion analysis of Miller-compensated three-stage amplifiers 84
A High-Speed Low-Power Output Buffer Amplifier for Large-Size LCD Applications 84
Resolution of a Current-Mode Algorithmic Analog-to-Digital Converter 84
A high-performance charge pump topology for very-low-voltage applications 84
Very-Low-Voltage Charge Pump Topologies for IoT Applications 83
Nonidealities of Tow-Thomas Biquads Using VOA- and CFOA-Based Miller Integrators 83
Guidelines for Designing Class-AB Output Stages 83
HIGHLY ACCURATE AND SIMPLE MODELS FOR CML AND ECL GATES 82
BEHAVIORAL MODEL OF ANALOG CIRCUITS FOR NONVOLATILE MEMORIES WITH VHDL-AMS 82
DOUBLE AND TRIPLE CHARGE PUMP FOR POWER IC - IDEAL DYNAMIC-MODELS TO AN OPTIMIZED DESIGN 82
Variations in Nanometer CMOS Flip-Flops: Part II – Energy Variability and Impact of Other Sources of Variations 82
Design procedure for two-stage CMOS transconductance operational amplifiers: A tutorial 82
Design of CMOS three-stage amplifiers for near-to-minimum settling-time 82
Totale 17.153
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Categoria #
all - tutte 123.387
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 123.387
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20211.858 0 0 0 0 748 42 257 21 288 14 231 257
2021/20223.166 425 451 9 40 538 5 450 103 312 32 105 696
2022/20234.582 473 164 62 309 392 845 28 880 1.205 28 128 68
2023/20242.496 106 440 100 106 58 281 51 95 15 542 417 285
2024/20257.708 240 851 505 524 1.817 813 209 316 505 872 446 610
2025/202614.035 900 1.534 9.059 1.055 1.487 0 0 0 0 0 0 0
Totale 38.493