IRIS
PALUMBO, Gaetano
 Distribuzione geografica
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Continente #
NA - Nord America 23.370
AS - Asia 9.851
EU - Europa 8.948
SA - Sud America 1.739
AF - Africa 1.287
OC - Oceania 59
Continente sconosciuto - Info sul continente non disponibili 18
AN - Antartide 2
Totale 45.274
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Nazione #
US - Stati Uniti d'America 22.655
SG - Singapore 4.970
CN - Cina 2.767
RU - Federazione Russa 2.203
IE - Irlanda 1.637
IT - Italia 1.499
UA - Ucraina 1.458
BR - Brasile 1.415
VN - Vietnam 806
CI - Costa d'Avorio 657
CA - Canada 598
FR - Francia 591
KR - Corea 326
FI - Finlandia 296
SE - Svezia 272
DE - Germania 240
NG - Nigeria 237
NL - Olanda 206
GB - Regno Unito 194
IN - India 194
SN - Senegal 190
HK - Hong Kong 143
AR - Argentina 120
BD - Bangladesh 89
CH - Svizzera 72
MX - Messico 65
ZA - Sudafrica 63
JP - Giappone 62
PL - Polonia 62
IQ - Iraq 59
UZ - Uzbekistan 56
EC - Ecuador 48
TR - Turchia 48
AU - Australia 46
AT - Austria 45
PK - Pakistan 45
ID - Indonesia 41
TW - Taiwan 39
CO - Colombia 38
VE - Venezuela 32
CZ - Repubblica Ceca 31
EG - Egitto 29
ES - Italia 29
SA - Arabia Saudita 26
CL - Cile 25
PH - Filippine 25
MA - Marocco 24
GR - Grecia 22
KE - Kenya 21
LB - Libano 21
PE - Perù 21
TN - Tunisia 21
PY - Paraguay 19
IL - Israele 17
AE - Emirati Arabi Uniti 16
JM - Giamaica 16
BJ - Benin 15
EU - Europa 15
DZ - Algeria 14
JO - Giordania 14
MY - Malesia 13
NZ - Nuova Zelanda 12
IR - Iran 11
BG - Bulgaria 10
OM - Oman 10
PT - Portogallo 10
UY - Uruguay 9
BE - Belgio 8
BO - Bolivia 8
KZ - Kazakistan 8
BY - Bielorussia 7
DK - Danimarca 7
ET - Etiopia 7
HN - Honduras 7
LT - Lituania 7
TH - Thailandia 7
AL - Albania 6
AZ - Azerbaigian 6
PA - Panama 6
RS - Serbia 6
MD - Moldavia 5
TT - Trinidad e Tobago 5
KG - Kirghizistan 4
NO - Norvegia 4
NP - Nepal 4
AM - Armenia 3
BN - Brunei Darussalam 3
CR - Costa Rica 3
DO - Repubblica Dominicana 3
GY - Guiana 3
HU - Ungheria 3
LU - Lussemburgo 3
PS - Palestinian Territory 3
SI - Slovenia 3
SV - El Salvador 3
XK - ???statistics.table.value.countryCode.XK??? 3
BB - Barbados 2
BH - Bahrain 2
EE - Estonia 2
GA - Gabon 2
Totale 45.233
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Città #
Dallas 9.402
Singapore 2.755
Santa Clara 2.217
Dublin 1.622
Jacksonville 1.534
Chandler 1.298
San Jose 1.082
Moscow 811
Ashburn 757
Abidjan 657
Boardman 638
Nanjing 515
Cambridge 449
Lawrence 447
Andover 436
Toronto 424
Hefei 416
Lauterbourg 406
Civitanova Marche 393
Beijing 342
Catania 328
Los Angeles 320
Seoul 320
Helsinki 283
Ho Chi Minh City 221
San Mateo 219
Des Moines 215
Chicago 207
Wilmington 195
Dakar 190
Houston 188
Hanoi 182
Dong Ket 178
Amsterdam 164
Nanchang 145
Shenyang 142
Lagos 139
São Paulo 131
Council Bluffs 128
Hebei 123
Hong Kong 113
Saint Petersburg 111
Changsha 105
Jiaxing 97
Ottawa 93
Tianjin 90
Buffalo 88
New York 85
Milan 83
Abuja 77
Grafing 61
The Dalles 58
Columbus 57
Rio de Janeiro 53
Palermo 50
Orem 43
Belo Horizonte 42
Seattle 41
Jinan 38
Chennai 36
Redondo Beach 36
Tokyo 36
Warsaw 36
Nuremberg 35
Montreal 33
Brasília 32
Hangzhou 31
Johannesburg 31
Munich 31
Washington 30
Phoenix 29
Haiphong 28
London 28
Rome 28
Brooklyn 27
Norwalk 27
Tashkent 27
Pune 26
Tremestieri Etneo 26
Naples 25
Denver 24
Liberty Lake 24
Piedimonte Etneo 24
Baghdad 23
Stockholm 23
Brno 22
Port Harcourt 21
Zhengzhou 21
Boston 20
Cairo 20
Da Nang 20
Bengaluru 19
Taizhou 19
Atlanta 18
Curitiba 18
Duncan 18
Mumbai 18
Porto Alegre 18
Kunming 17
Lima 17
Totale 33.046
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Nome #
A 0.003-mm2 50-mW Three-Stage Amplifier Driving 10-nF with 2.7-MHz GBW 3.684
0.5-v frequency dividers in folded mcml exploiting forward body bias: Analysis and comparison 3.548
Mixed Full Adder topologies for high-performance low-power arithmetic circuits 240
Design guidelines of CMOS class-AB output stages: a tutorial 213
A 1-V CMOS Output Stage with High Linearity 207
A Bulk Current Regulation Technique for Dual-Branch Cross-Coupled Charge Pumps 206
1.5-V CMOS CCII+ WITH HIGH CURRENT-DRIVING CAPABILITY 188
1.2-V CMOS op-amp with a dynamically biased output stage 188
A Clock Boosted Charge Pump with Reduced Rise Time 186
A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers 180
A 1.5-V high drive capability CMOS op-amp 180
1.5V power supply CMOS voltage squarer 175
1.2-V CMOS OUTPUT STAGE WITH IMPROVED DRIVE CAPABILITY 172
1.5-V High-Drive Second Generation Current Conveyor 171
A 1.5 CMOS Voltage Multiplier 169
A 50-mA 1-nF Low-Voltage Low-Dropout Voltage Regulator for SoC Applications 164
A CMOS CURRENT AMPLIFIER 159
195-nW 120-dB Subthreshold CMOS OTA Driving up to 200 pF and Occupying only 4.4·10-3 mm2 159
A Charge Loss Aware Advanced Model of Dickson Voltage Multipliers 156
Dynamic-biased capacitor-free NMOS LDO voltage regulator 154
1V CMOS output stage with excellent linearity 154
A 1.35-V Sense Amplifier for Non Volatile Memories based on Current Mode Approach 153
A New Method for Harmonic Distortion Analysis in Class-AB Stages 149
2-MHz GBW CMOS OTA for 250 pF to 1.25 nF capacitive load 149
An Accurate Ultra-Compact I–V Model for Nanometer MOS Transistors With Applications on Digital Circuits 143
A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads 143
Design of low-power high-speed bipolar frequency dividers 139
Analysis and optimization of a novel CMOS multiplier 135
Design of an Nth order Dickson voltage multiplier 135
Signal Amplifiers 134
A Schmitt trigger by means of CCII+ 132
Autonomous Energy-Efficient Wireless Sensor Network Platform for Home/Office Automation 132
Robust design of CMOS amplifiers oriented to settling-time specification 131
"Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems" (di Keh-La Lin, A. Kemna, B. Hosticka), in IEEE Circuits & Devices Magazine 131
PERFORMANCE EVALUATION OF ADIABATIC GATES 130
Area-efficient design of three- and four-stage voltage multipliers for power integrated circuits 130
A New Advanced RNMC Technique with Dual-Active Current and Voltage Buffers for Low-Power High-Load Three-Stage Amplifiers 130
A New Accurate Analytical Expression for the SiPM Transient Response to Single Photons 129
Advances in Reversed Nested Miller Compensation 126
CML RING OSCILLATORS: OSCILLATION FREQUENCY 124
DOUBLE AND TRIPLE CHARGE PUMPS WITH MOS DIODES - DYNAMIC-MODELS TO AN OPTIMIZED DESIGN 124
A New Enhanced PSPICE Implementation of the Equivalent Circuit Model of SiPM Detectors 122
Optimized Design of an N-th Order Dickson Voltage Multiplier 121
Integrated Quenching-and-Reset Circuit for Single-Photon Avalanche Diodes 121
A high-performance very low-voltage current sense amplifier for nonvolatile memories 120
An Efficient RNM Compensation Topology with Voltage Buffer and Nulling Resistors for Large-Capacitive-Load Three-Stage OTAs 120
Introduzione ai Convertitori A/D del tipo Sigma-Delta 120
Variations in Nanometer CMOS Flip-Flops: Part I – Timing and Impact of Process Variations 119
AN ACCURATE OFFSET–COMPENSATED CURRENT COMPARATOR 119
A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETs 119
Introduzione ai Dispositivi Elettronici 118
A Detailed Analysis of Power-Supply Noise Attenuation in Bandgap Voltage References 118
Optimized Charge Pump with Clock Booster for Reduced Rise Time or Silicon Area 118
A Novel Low-Power High-Speed Rail-to-Rail Class-B Buffer Amplifier for LCD Output Drivers 117
A Fuzzy A/D Converter by Means of Current-Mode Approach 117
Class-AB CMOS output stages suitable for low-voltage amplifiers in nanometer technologies 116
Approach to the design of low-voltage SC filters 115
Analytical Figure of Merit Evaluation of RNMC Networks for Low-Power Three-Stage OTAs 115
A compensation strategy for two-stage CMOS opamps based on current buffer 113
A Fuzzy Controller for Step-Up DC/DC Converters 113
Pseudo-Random Sequence Generators with Improved Inviolability Performance 112
DOUBLE AND TRIPLE CHARGE PUMP FOR POWER IC - IDEAL DYNAMIC-MODELS TO AN OPTIMIZED DESIGN 111
A High-Speed Low-Power Output Buffer Amplifier for Large-Size LCD Applications 111
Three-stage single-miller CMOS OTA driving 10 nF with 1.46-MHz GBW 111
Guest editorial 110
Design procedures for three-stage CMOS OTAs with nested-Miller compensation 109
A New Compact Low-Power High-Speed Rail-to-Rail Class-B Buffer for LCD Applications 109
Behavioral modeling of statistical phenomena of single-photon avalanche diodes 108
The noise performance of Miller CMOS operational amplifiers with current-buffer frequency compensation 108
Variations in Nanometer CMOS Flip-Flops: Part II – Energy Variability and Impact of Other Sources of Variations 108
CMOS CURRENT AMPLIFIERS 108
DESIGN METHODOLOGY AND ADVANCES IN NESTED-MILLER COMPENSATION 108
IMPROVED BEHAVIORAL AND DESIGN MODEL OF AN N-TH ORDER CHARGE PUMP 107
DOUBLE AND TRIPLE CHARGE PUMP FOR POWER IC - DYNAMIC-MODELS WHICH TAKE PARASITIC EFFECTS INTO ACCOUNT 107
An approach to test the open-loop parameters of feedback amplifiers 107
Guidelines for Designing Class-AB Output Stages 106
Single-miller all-passive compensation network for three-stage OTAs 105
HIGH LINEARITY CMOS CURRENT OUTPUT STAGE 104
AN OPTIMIZED COMPENSATION STRATEGY FOR 2-STAGE CMOS OP AMPS 104
GAIN-COMPENSATED SAMPLE-AND-HOLD CIRCUIT FOR HIGH-FREQUENCY APPLICATION 104
Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time 104
A Generalization of Miller Formulae for Nonlinear Feedback Networks 104
Design procedure for two-stage CMOS transconductance operational amplifiers: A tutorial 104
MODELING OF SOURCE COUPLED LOGIC GATES 103
Nonidealities of Tow-Thomas Biquads Using VOA- and CFOA-Based Miller Integrators 103
Optimized Active Single-Miller Capacitor Compensation with Inner Feedforward for Very High-Load Three-Stage OTAs 103
Switched capacitor compatible minimum-maximum function 103
Improved Power-Efficient RNMC Technique with Voltage Buffer and Nulling Resistors for Low-Power High-Load Three-Stage Amplifiers 102
Linear distribution of capacitance in Dickson charge pumps to reduce rise time 102
A high-performance charge pump topology for very-low-voltage applications 102
Charge Pumps for Ultra-Low-Power Applications: Analysis, Design and New Solutions 102
Very-Low-Voltage Charge Pump Topologies for IoT Applications 101
Memorie Ferroelettriche 101
NEW CMOS CURRENT MIRRORS WITH IMPROVED HIGH-FREQUENCY RESPONSE 101
Design and Comparison of Very Low-Voltage CMOS Output Stages 101
Power Supply Rejection of Widlar Bandgap Voltage Reference 101
A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold Lowering 101
Simple and Accurate Model for the Propagation Delay in MCML Gates 100
Improved Low-Power High-Speed Buffer Amplifier with Slew-Rate Enhancement for LCD Applications 100
Distortion analysis of Miller-compensated three-stage amplifiers 100
Totale 19.788
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Categoria #
all - tutte 140.246
article - articoli 0
book - libri 0
conference - conferenze 0
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 140.246
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021488 0 0 0 0 0 0 0 0 0 0 231 257
2021/20223.166 425 451 9 40 538 5 450 103 312 32 105 696
2022/20234.582 473 164 62 309 392 845 28 880 1.205 28 128 68
2023/20242.496 106 440 100 106 58 281 51 95 15 542 417 285
2024/20257.708 240 851 505 524 1.817 813 209 316 505 872 446 610
2025/202621.732 900 1.534 9.059 1.055 2.309 2.393 1.896 467 1.089 736 294 0
Totale 46.190